Econet hardware circuit description

Apart from differences in physical size the circuits for all Econet interfaces are largely the same and a generalised circuit description is given here with component references taken from the Eurocard circuit diagram. When fully populated, Econet interface cards consume around 250 mA from a single +5 volt power supply. This supply is normally provided on the card connector in the computer being interfaced to the network. All Econet interfaces are based upon the MC6854 Advanced Data Link Controller IC, other support functions for it are network line drivers and receivers, network clock generators, network collision detectors and station identifiers.

Address decoding

The Econet card for the ATOM is decoded on the ATOM PCB at memory address B400 (hex). The Econet Eurocard has decoding circuits on it which select memory address 1940 (hex). There are then five significant addresses above these bases which contain the following registers: -

				ATOM card	Eurocard
	6854	register 1	B400		1940
	6854	register 2	B401		1941
	6854	register 3	B402		1942
	6854	Tx/Rx Data reg.	B403		1943
	Station	identification	B404		1944

Network clock generation

One station per network must generate the network clock which synchronizes all data transfers over the network. The clock generation circuit consists of IC 6, IC 7 and associated passive components. One gate of IC 9 generates a 3 MHz signal locked to the system clock. R 31 should be selected to give a symmetrical 3 MHz signal. The clock transmitter is enabled by linking pin 9 of IC 4 to +5 volts on the card, and it is disabled on all other cards by linking this pin to 0 volts. Refer to the card component layout diagram for the position of these links which must be soldered in during installation.

The clock frequency must also optimised for the network, this is done by means of links to IC's 6 and 7. These links first select a starting frequency, for instance 500 kHz, and then another link selects either a divide by 2 or a divide by 4, giving 250 or 125 kHz clock speeds. The clock frequency in kHz is also the rate of data transfer over the network in kilo-bits per second or kBaud. The clock frequency of the network is related to the length of the network in that longer networks must have slower clocks due to the finite time signals take to travel over the network and the requirement that all stations on a network are synchronized to the same clock edge. As a guide here are a few network lengths and recommended maximum clock frequencies:-

	Length	Frequency
	300m	250 kHz
	830m	214 kHz
	1.7 km	107 kHz

In general a lower clock frequency leads to better system noise immunity and improved reliability, hence in electrically noisy environments a low clock speed should be choosen. There is a limit on the speed tolerance of the software, version 1 will not operate above 210 kHz or below 100 kHz. With regard to reliability the section on network termination should be consulted. The following table gives the frequencies provided by IC 7 and the network clock speeds available from them by selecting divide by 2 or divide by 4:-

		/2	/4
	600k	300k	150k
	500k	250k	125k
	428k	214k	107k
	375k	187k	93k
	333k	166k	83k
	300k	150k	75k

Station identification

The identity number of each station is set up in hardware by links to IC 8. IC 8 is an octal buffer which when enabled feeds the cards station ID to the computer bus. Each link codes a bit in an eight bit binary number allowing any station ID in the range 0 to 255 to be set up. if a link is left open then the bit is a one, when a link is made the bit is a zero. Hence all links open corresponds to station ID 255, and all links made to station ID 0. Each station must have a unique identity and some indentities are associated with specific functions on the network. Station ID zero is reserved for broadcast signals and should not be used. Station ID 255 is reserved at present for the file server, and 235 for the printer server. Wire links must be soldered to each network station card during installation, a sugested scheme for number allocation is to number normal user stations from one upwards and to number special stations and servers from 255 downwards.


The Advanced Data Link Controller IC deals with the construction of bit frames to be sent over the net. Frame describes a series of bits which are ordered in a particular way, the bits are grouped into 8 bit bytes and the ADLCs perform parallel to serial and serial to parallel conversions. The Econet software generates packets of information to be transmitted and it communicatens with the ADLC via the computer bus. These packets contain the source and destination station IDs and the data to be transmitted, the ADLC then puts this information packet into a frame of bits which also has start and finish flags and a Cyclic Redundancy Check.

Reset interrupt

Some systems will require the Econet software to be executed at switch on so that load and save vectors netc are redirected automatically, the ATOM card has this facility. The system reset signal is taken to the ADLC IC and on reset its Not Data Terminal Ready signal goes high. This switches Q1 on, which pulls the NIRQ line low causing an interrupt. On interrupt the ATOM executes its Econet initialisation software from location A000 (hex). As part of the initialisation the NDTR signal is switched low which removes this interrupt signal.


The transmission of data and clock onto the network is via a 75159 dual differential line driver, these devices are to the RS 422 specification and they can source or sink 40mA. Differential line techniques ensure both minimal radiation and high noise immunity for the network. The clock transmitter is enabled by a link as described in the clock details. The data driver is enabled by a Not Request To Send signal from the ADLC when it wishes to transmit. When disabled or powered down the buffers have high impedence outputs and so stations may be left connected to the network even when they are not in use.


The reception of data and clock signals from the network is accomplished using an LM 319 dual fast differential comparator. The receiver circuits are designed to give common mode signal rejection and hysteresis thus providing noise immunity. The network clock is received to clock the ADLC for both reception and transmission of data.

When no station is driving the network the ADLC needs to be able to reliably detect that the network is undriven and therefore free for use, to this end undriven data lines must appear as a continuous stream of logic ls and not random noise which could be taken for some other stations data. The network terminators bias the lines so that receivers receive a logic 1 in the absence of a logic 0 being transmitted onto the network. ADLCs use a technique called Zero Bit Insertion and when they are transmitting a logic 0 is seen every few bits, this effect is both created and removed by the ADLCs and it need not concern the user. As a consequence of the biased receivers and the ZBI technique a station coming onto the network and wishing to transmit monitors the data line and knows that the network is free if it receives 15 consecutive logic 1s.

Collision detection

One characteristic of broadcast networks like the Econet is that collisions occur when two stations both choose to transmit on to the network at the same time. This is largely avoided by stations testing that no other station is driving the network before commencing transmission, however a period of time exists between a station detecting an undriven network and then enabling its driven r in order to start transmission. During this period another station may begin to transmit and a collision will occur, the SN75159 driver circuit is not damaged in this event but the data on the network is corrupt. Every station card on the network carries a collision detector circuit which informs its ADLC that a ncollision has ocurred, the station can then abort its attempt to transmit and wait for a period of time before trying again.

The collision detection circuit is based on an LM319 dual comparator which is used to compare each of the data signal lines with the common mode signal on the line. When stations collide their differential drivers will short out and the data lines will be forced to the same voltage. If one or the other of the two data wires is above the common mode signal by more than 1 volt the data is assumed valid, but if they both drop below the common mode voltage together a collision is deemed to have occured. The comparators have open collector outputs, the two used in the collision detect circuit have their outputs arranged in a wired or configuration giving the Data Valid signal when there are no collisions.

This method of collision detection will also flag an invalid data line condition on Data Valid when no station is driving the lines, as the voltage on both of the data wires will drop. However this does not matter as the ADLC only looks for collisions when it is driving the lines.

Clock valid monostable

The ADLC should only attempt to transmit when the data lines are free and there is a valid clock to clock the data onto the line. The valid clock condition is sensed using a retriggerable monostable which only produces a Data Carrier Detect signal when the card is connected to a clocked network. Data Valid and Data Carrier Detect are anded together to give a Not Clear To Send signal for the ADLC. The ADLC can differentiate between the unconnected network and not data valid conditions as a Not Data Carrier Detect signal is also fed to it from the monostable.